1. Field of the Invention
The present invention relates to a monolithic semiconductor device (chip) including repetitive cells.
2. Description of the Related Art
For example, a flash or parallel-type analog/digital (A/D) converter is constructed by a large number of repetitive cells. That is, such an A/D converter is constructed by comparators for comparing an analog input voltage with reference voltages, latch circuits for latching the output signals of the comparators, and a binary encoder for encoding the output signals of the latch circuits. In this case, the comparators form repetitive cells in a monolithic semiconductor device. Each of the comparators is constructed by one differential pair and one current source for supplying a current thereto. This will be explained later in detail.
In the above-mentioned A/D converter, when mismatches resulting from deviations from nominal occur between the repetitive cells, the differential and integral linearity would deteriorate.
In order to suppress the above-mentioned mismatches between the repetitive cells, an impedance network such as a resistor is connected between outputs of differential pairs (see: U.S. Pat. No. 5,175,550). This also will be explained later in detail.
In the above-described prior art, however, although the mismatches resulting from deviations from nominal occurring between the differential pairs of the comparators can be suppressed, the mismatches resulting from deviations from nominal occurring between the current sources of the comparators cannot be suppressed, which still would deteriorate the differential and integral linearity of the above-mentioned A/D converter.